FPGA Circuit Design Engineer job opportunity at Altera Corporation.

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DatePosted 30+ Days Ago bot
Altera Corporation FPGA Circuit Design Engineer
Experience: 8-years
Pattern: full-time
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loacation San Jose, California, United States, United States Of America
loacation San Jose, Cali..........United States Of America

Job Details: Job Description: About Altera For decades, Altera has been at the forefront of programmable logic technology, empowering innovators across data center, communications, automotive, aerospace, and industrial markets. Our cutting-edge FPGA, SoC, and software solutions enable customers to solve the world’s most complex engineering challenges. At Altera, you’ll work alongside world-class engineers in a collaborative, fast-paced environment focused on pushing the boundaries of semiconductor technology. About the Role We are seeking an experienced FPGA Circuit Design Engineer to join Altera’s advanced FPGA development team. In this role, you will be responsible for the design, development, and optimization of high-performance digital and mixed-signal circuits used in next-generation FPGA products. You will work closely with architecture, verification, physical design, and silicon validation teams to deliver robust, power-efficient, and scalable circuit solutions from concept through silicon. This position is ideal for a highly motivated engineer who thrives in a technically deep environment and is passionate about building industry-leading programmable logic devices. Responsibilities Design and develop high-performance digital and mixed-signal circuits for FPGA core   and Clock Distribution Contribute to circuit architecture definition, micro-architecture, and feasibility studies for next-generation FPGA products. Perform transistor-level design, simulation, and optimization for   performance   , power, area, and reliability. Develop schematics and support layout teams by  optimizing layout for power , performance and area   that  include  layout reviews and signoff. Work within team to help  silicon debugs   Collaborate cross-functionally with architecture, logic design, verification, physical design, process technology, and product engineering teams. Salary Range   The pay range below is for Bay Area California only. Actual salary may vary based on   a number of   factors including job location, job-related knowledge, skills, experiences,   trainings , etc. We also offer incentive opportunities that reward employees based on individual and company performance.    $127,400 - $184,000   USD     We use artificial intelligence to screen, assess, or select applicants for the position.   Applicants must be eligible for any required U.S. export authorizations .   Qualifications: Minimum Qualifications Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field, plus 8+ years of industry experience in circuit design within the semiconductor industry. Experience in digital circuit design at the transistor and block level and  in generation of schematics  from RTL  Experience designing circuits in advanced CMOS process nodes and understanding  impact of layout in power and  performance . Experience using circuit simulation and layout tools (e.g., SPICE-based simulators - HSPICE , FINESIM,WAVEVIEW , Virtuoso) Experience with PRIMETIME  and lib characterization for  advanced CMOS process nodes Familiarity with modern silicon design tools /checks -  Totem, UPF , VCS , LINT Experience  with  Python, GIT HUB,  TCL/TK Job Type: Regular Shift: Shift 1 (United States of America) Primary Location: San Jose, California, United States Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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