Senior Director of Post-Silicon Validation job opportunity at Altera Corporation.

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DatePosted 30+ Days Ago bot
Altera Corporation Senior Director of Post-Silicon Validation
Experience: 10-years
Pattern: full-time
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loacation San Jose, California, United States, United States Of America
loacation San Jose, Cali..........United States Of America

Job Details: Job Description: About Altera Altera is a leading provider of FPGAs, SoCs, and semiconductor solutions powering innovation across AI, networking, high-performance computing, and embedded systems. We are committed to delivering world-class silicon products through rigorous validation and engineering excellence. Role Overview Altera is seeking a visionary Senior Director of Post-Silicon Validation to lead and drive all aspects of post-silicon validation across multiple product lines. This strategic leadership role is responsible for defining validation roadmaps, ensuring robust silicon bring-up, and enabling high-quality product launches. Key Responsibilities Strategic Leadership: Define and implement Altera’s post-silicon validation strategy, roadmap, and execution plans to meet quality and time-to-market goals. End-to-End Validation Ownership: Oversee the full post-silicon validation lifecycle—from initial bring-up to high-volume production ramp-up. Cross-Functional Collaboration: Partner with design, verification, software, test, and manufacturing teams to ensure seamless validation and debug processes. Technical Excellence: Lead efforts in system-level debugging, performance characterization, and validation methodology development. Process Optimization: Establish and continuously improve validation tools, automation frameworks, and lab infrastructure. Risk Management: Identify and mitigate technical risks, ensuring robust contingency planning and issue resolution. Team Leadership: Build, mentor, and lead a high-performing validation team, fostering innovation and collaboration. Executive Communication: Provide regular updates to senior leadership on validation progress, risks, and resolutions. Compliance & Standards: Ensure validation practices align with industry standards and regulatory requirements. Salary Range  The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance. $221,500 - $326,350 USD  *We use artificial intelligence to screen, assess, or select applicants for the position.* #LI-MD1 Qualifications: Required Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. 10+ years of experience in silicon validation, with 5+ years in a leadership role. Proven track record managing large-scale validation programs across multiple product lines. Deep expertise in post-silicon validation methodologies, high-speed interfaces, power management, and system-level debug. Strong leadership and cross-functional collaboration skills. Experience with industry-standard validation tools and lab equipment. Excellent communication and problem-solving abilities. Preferred Qualifications Experience in high-performance computing, AI accelerators, or networking silicon products. Knowledge of firmware validation, statistical data analysis, and test automation. Familiarity with Agile development and modern program management practices. Job Type: Regular Shift: Shift 1 (United States of America) Primary Location: San Jose, California, United States Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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