Senior Staff Digital Design Engineer job opportunity at Marvell Technology, Inc..

Home Jobs In Vietnam Tag: Job Senior Staff Digital Design Engineer position at Marvell Technology, Inc.


DatePosted 10 Days Ago bot
Marvell Technology, Inc. Senior Staff Digital Design Engineer
Experience: 5-years
Pattern: full-time
Country:
apply Apply Now
Salary:
Status:

Job

Copy Link Report
degreeOND
loacation Ho Chi Minh, Vietnam
loacation Ho Chi Minh....Vietnam

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact As a Digital IC Design Senior Staff Engineer with Marvell, you’ll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. You’ll be part of a digital team of about eight people making a big impact on this organization, working on ultra-dense and performance ASIC. This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell. The customers served by this team are often other chip companies and big tech companies, familiar names to all candidates. What You Can Expect Job Responsibilities:  Become a member of a world‐class design team. You will have an opportunity to design the latest high‐performance AI silicon and other critical high speed interface (PCIe, CXL, UA link) IP designs for Marvell’s core products. All team members participate in circuit architecture, RTL implementation, design review, layout, and silicon DV and validation in the following areas: Develop next generation silicon IP utilizing advanced digital technologies. Perform architecture discussion and design. Review architecture and define test plan, including RTL coding and debug. Support firmware team to develop production firmware code. Support validation team and FAE to trouble shoot for our silicon to find root cause and provide fix. Review design documentation, description and information to internal and external customers. What We're Looking For Requirements: Minimum BSEE plus 5 years of design experience in one of the following areas: Analyze and improve design architecture and block-level IP microarchitecture Implement RTL design with Hardware Description Language (Verilog, SystemVerilog) On-Chip bus protocols knowledge: AXI, AHB, APB Performing Lint, CDC check, Timing closure, coverage closure analysis Basic understanding of UVM based test bench Basic understanding of scripting/programming language with PERL/Python, TCL and C/C++ Preferred:  Experience as a technical lead is a plus. Additional Compensation and Benefit Elements Competitive salary, plus 13th-month salary and performance-based bonus RSUs (Restricted Stock Units) for new joiners and on-going annually Premium health & accident insurance for you and your family (spouse and children) Annual medical check-up at a designated hospital arranged by Marvell Generous paid leave policies: 15 annual leave days, 3 Recharge periods per year (company-wide off-work from Friday to Monday), 5 paid sick leave days, 3 days of volunteer time-off and 11 public holidays Exciting Employee Events: Participate in fun activities throughout the year such as team birthdays, sports tournaments, company trips, mid-autumn, appreciation week, charity, health seminars, year-end party, and more. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Interview Integrity  To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-UN1

Other Ai Matches

AMS CAD - ML/AI Developer Intern Applicants are expected to have a solid experience in handling Job related tasks
Engineering Program Manager Applicants are expected to have a solid experience in handling Job related tasks
Hardware & Silicon Validation Principal Engineer Applicants are expected to have a solid experience in handling Job related tasks
Manager of Procurement - semiconductor manufacturing/OSAT Applicants are expected to have a solid experience in handling Job related tasks
Advanced Packaging SI/PI Senior Staff Engineer Applicants are expected to have a solid experience in handling Job related tasks
Pricipal System Engineer/PCB Design - CPU/SoC Devices Applicants are expected to have a solid experience in handling Job related tasks
Flow/AI Intern - Master's Degree Applicants are expected to have a solid experience in handling Job related tasks
Director – FP&A Systems Applicants are expected to have a solid experience in handling Job related tasks
AV Events and Media Specialist Applicants are expected to have a solid experience in handling Job related tasks
Senior Counsel (Vietnam Legal Lead) Applicants are expected to have a solid experience in handling Job related tasks
PHY Digital Lead Applicants are expected to have a solid experience in handling Job related tasks
Principal Optical Engineer Applicants are expected to have a solid experience in handling Job related tasks
Analog IC Design Engineer Intern Applicants are expected to have a solid experience in handling Job related tasks
Senior Financial Analyst Applicants are expected to have a solid experience in handling Job related tasks
Advanced Packaging SI/PI Staff Engineer Applicants are expected to have a solid experience in handling Job related tasks
DSP Architecture System Modeling Engineer Applicants are expected to have a solid experience in handling Job related tasks
Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Analog Layout Intern Applicants are expected to have a solid experience in handling Job related tasks
Staff Engineer, Analog IC Design Applicants are expected to have a solid experience in handling Analog IC Design related tasks
Technical Director, Physical Design Applicants are expected to have a solid experience in handling Physical Design related tasks
Principle FAE, ASIC Applicants are expected to have a solid experience in handling ASIC related tasks
Senior Staff Engineer, Physical Design Applicants are expected to have a solid experience in handling Physical Design related tasks
Systems Application Engineer Applicants are expected to have a solid experience in handling Job related tasks