Senior Principal Digital IC Design Engineer job opportunity at Marvell Technology, Inc..

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DatePosted 13 Days Ago bot
Marvell Technology, Inc. Senior Principal Digital IC Design Engineer
Experience: 15-years
Pattern: full-time
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loacation Santa Clara, CA, United States Of America
loacation Santa Clara, C..........United States Of America

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact As a Senior Principal Digital IC Design Engineer at Marvell, you will be part of the DCE – Connectivity Business Group, contributing to the development of cutting-edge hardware solutions. As a member of our R&D team, you’ll play a pivotal role in designing and implementing world-class ASICs that power products for industry-leading customers. This is an opportunity to collaborate with top-tier technologists and grow your career in an environment that values innovation, transparency, and execution. What You Can Expect Collaborate with systems and architecture teams to define SoC-level specifications , including performance, power, area, and feature requirements. Translate high-level product requirements into detailed micro-architecture specifications for subsystems and IP blocks. Lead RTL development and integration , ensuring modularity, reusability, and compliance with design guidelines. Create modular and reusable design components to support scalable and maintainable architectures. Partner with DV teams to define and review verification plans , including functional, coverage-driven, and power-aware strategies. Support pre-silicon bring-up activities , including FPGA prototyping and emulation. Support post-silicon validation , working closely with lab teams to resolve complex issues and validate performance targets. Conduct detailed design reviews with cross-functional teams and contribute to the continuous improvement of design and verification methodologies. Supervise and mentor junior digital design engineers , providing technical leadership and guidance. What We're Looking For Bachelor’s degree in Computer Science, Electrical Engineering, or related fields with 15+ years of professional experience , or Master’s/PhD in Computer Science, Electrical Engineering, or related fields with 10+ years of experience . Minimum of 10 years of industry experience in developing, implementing, and testing high-performance communications ASIC products. Extensive experience in RTL design , including verification, synthesis, and timing closure. Strong background in embedded microcontroller systems . Proficiency with UNIX-based EDA tools (e.g., VCS, PrimeTime, Design Compiler, CDC) and deep understanding of ASIC design flows. Familiarity with PHY/MAC layer communication protocols such as Ethernet, PCIe, UA Link, SUE, or ESUN. Knowledge of signal processing circuit structures or error-correcting code architectures is a plus. Experience with industry-standard interfaces such as MDIO, I2C, I3C, SPI, and SMBus is a plus. Proven track record in project leadership , with the ability to thrive in a fast-paced, dynamic environment and manage multiple priorities effectively. Expected Base Pay Range (USD) 182,360 - 273,200, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements   Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com . Interview Integrity  To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-MM1

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