Principal Engineer Physical Design job opportunity at Marvell Technology, Inc..



DatePosted 30+ Days Ago bot
Marvell Technology, Inc. Principal Engineer Physical Design
Experience: 15-years
Pattern: full-time
apply Apply Now
Salary:
Status:

Job

Copy Link Report
degreeOND
loacation Bucharest, Romania, Romania
loacation Bucharest, Rom..........Romania

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact Built on decades of expertise and execution, Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you’ll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, and networking applications. What You Can Expect As a senior leader in the central physical design team, you will: Shape the long-term vision for physical design capabilities and infrastructure in alignment with company-wide technology strategy. Lead RTL-to-GDSII implementation for multiple SoC programs, overseeing synthesis, floorplanning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, and physical verification (DRC/LVS). Provide strategic leadership and technical direction to physical design teams, ensuring successful and timely tapeouts of complex, high-performance SoCs. Mentor and develop engineering talent, fostering a culture of innovation, collaboration, and continuous improvement. Oversee team structure, hiring, performance management, and career development to build and retain a high-performing physical design organization. Drive cross-functional collaboration with design teams to influence design decisions and ensure successful project execution. Navigate and resolve cross-functional conflicts effectively, fostering alignment and maintaining momentum across diverse teams. Drive the development and adoption of next-generation physical design methodologies, flows, and automation to improve productivity and design quality. Manage project schedules, resources, and risk, ensuring alignment with business goals and customer requirements. Represent the physical design function in cross-org and executive-level discussions, contributing to long-term technology and product strategy. Collaborate with EDA vendors and internal CAD teams to evaluate and deploy new tools and technologies. What We're Looking For Bachelor’s, Master’s, or PhD degree in Electronics, Computer Engineering, or a related field. 15+ years of progressive experience in back-end physical design and verification, including significant leadership roles. Proven track record of leading and scaling physical design teams, managing complex SoC projects, and delivering high-quality tapeouts under tight schedules. Deep expertise in hierarchical physical design strategies, methodologies, and advanced process node challenges. In-depth understanding of current design technologies used in major foundries. Strong understanding of ASIC design flow, RTL integration, synthesis, and timing closure. In-depth knowledge of EDA tools and flows. Proficient in automation and scripting using Tcl, Python, or Perl to enhance design efficiency and flow robustness. Strong communication and collaboration skills, with the ability to influence cross-functional teams and executive stakeholders. Experience in developing and deploying advanced physical design methodologies and flows. Familiarity with AI/ML-driven optimization in physical design tools is a plus. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Interview Integrity   As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.   Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-AB1

Other Ai Matches

Principal Engineer - Memory Compiler Circuit Design Applicants are expected to have a solid experience in handling Job related tasks
Staff Test Engineer (Optical Module) Applicants are expected to have a solid experience in handling Job related tasks
Sr. Staff Engineer, Package Engineering Applicants are expected to have a solid experience in handling Package Engineering related tasks
Principal Digital IC Design Engineer Applicants are expected to have a solid experience in handling Job related tasks
Design for Test Engineering Intern Applicants are expected to have a solid experience in handling Job related tasks
Senior Staff Physical Verification CAD engineer - EDA Tools Applicants are expected to have a solid experience in handling Job related tasks
Analog Mixed Signal Design Engineer, Principal Applicants are expected to have a solid experience in handling Principal related tasks
Staff Engineer- Firmware Development (HDD) Applicants are expected to have a solid experience in handling Job related tasks
Hardware Validation (Test Solutions) Engineer Applicants are expected to have a solid experience in handling Job related tasks
Test Engineer Intern - Bachelor's Degree Applicants are expected to have a solid experience in handling Job related tasks
AI Developer Platforms (Security) Applicants are expected to have a solid experience in handling Job related tasks
Software Developer Engineer in Test Applicants are expected to have a solid experience in handling Job related tasks
Senior Principal Engineer, Reliability Applicants are expected to have a solid experience in handling Reliability related tasks
Senior Business Operations Analyst - Finance, Data Analytics, Costing and Pricing Applicants are expected to have a solid experience in handling Data Analytics, Costing and Pricing related tasks
Package Engineering Intern - Ph. D Degree Applicants are expected to have a solid experience in handling Job related tasks
Hyperscale Global Account Manager Applicants are expected to have a solid experience in handling Job related tasks
Sr. Principal Photonics Engineer Applicants are expected to have a solid experience in handling Job related tasks
Analog Engineer Intern - PhD Applicants are expected to have a solid experience in handling Job related tasks
Analog Engineer Intern - PhD Applicants are expected to have a solid experience in handling Job related tasks
Product Manager/Product Line Manager - Custom Silicon Solutions / ASIC / System Management and Security Applicants are expected to have a solid experience in handling Job related tasks
Senior Analog/Mixed-Signal Design Engineer - RF/SiPho/TIA/CMOS/SiGe Applicants are expected to have a solid experience in handling Job related tasks
Logic design Eng Applicants are expected to have a solid experience in handling Job related tasks
Senior Staff Design, Mixed-Signal Design Applicants are expected to have a solid experience in handling Mixed-Signal Design related tasks