Senior Development Engineer – Photonic Devices / VCSEL Epitaxy (m/f/d) job opportunity at Western Digital.



Date2026-03-02T23:15:46.087Z bot
Western Digital Senior Development Engineer – Photonic Devices / VCSEL Epitaxy (m/f/d)
Experience: General
Pattern: Full-time
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loacation Ulm, Baden-Württemberg, Germany
loacation Ulm, Baden-Wür..........Germany
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Job DescriptionThe Senior Development Engineer will drive the design and optimization of epitaxial stacks for VCSEL and related photonic device structures. The role focuses on translating device‑level requirements into robust epitaxial designs, using advanced semiconductor physics and numerical simulations to guide development and optimize performance, yield, and reliability. This position is ideal for someone with a strong academic and/or R&D background in semiconductor physics and photonic devices who wants to work at the interface of epitaxy, device design, and product development. Key ResponsibilitiesDesign and simulate epitaxial layer stacks for VCSEL and other photonic device structures to meet optical, electrical, and thermal device requirements.Develop and refine device and epitaxy simulation models (e.g., optical cavity / mode simulations, carrier transport, thermal behavior) to support architecture decisions.Translate system and device requirements into epitaxial specifications (materials, layer sequences, thicknesses, doping profiles).Work closely with epitaxy, process, and device characterization teams to:Define experiments and DOEs. Interpret measurement and reliability data. Iterate designs based on feedback from wafer- and device‑level results.Contribute to device architecture and development strategies, including roadmaps for performance, reliability, and manufacturability improvements.Analyze and correlate simulation, epitaxial, and device performance data to identify root causes and optimization paths.Prepare and present technical reports, design reviews, and development status updates for internal stakeholders.Collaborate in a multi‑disciplinary, international R&D environment, coordinating with colleagues across different locations and time zones (with substantial overlap to EU working hours).Mentor junior engineers and students in topics such as semiconductor device physics, simulation methodology, and data analysis.

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