ASIC Analog Layout Engineer (m/f/d) - REF5390S job opportunity at Aumovio.

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Date2026-04-23T14:38:44.137Z bot
Aumovio ASIC Analog Layout Engineer (m/f/d) - REF5390S
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Pattern: Full-time
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loacation Guerickestraße 7, Frankfurt am Main, Hesse, Germany
loacation Guerickestraße..........Germany
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Job DescriptionAs an ASIC Layout Engineer (m/f/diverse) for AESS (Advanced Electronics & Semiconductor Solutions), you will be responsible for the top-level integration of analog and mixed-signal ICs. You will drive the layout development process, ensuring robust, DRC-compliant designs with optimal area utilization. You will collaborate closely with analog circuit designers and other layout engineers to deliver high-quality silicon.Key ResponsibilitiesDrive the top-level layout integration of analog/mixed-signal chips (analog on top)Define toplevel floorplan, padframe design and bonding diagrams in coordination with other domainsCoordinate with other layouters to define floorplans according to the chip top levelGenerate and integrate analog layouts at block and chip levelPerform pin placement, parasitic extraction, and layout optimizationEnsure compliance with DRC, LVS, and support tape-out activitiesCollaborate with design engineers to meet speed, area, power, DFM, ESD, and EMC requirements

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