Sr Staff/Staff/Senior Engineer– IP Design Verification job opportunity at Renesas Electronics.

Home Jobs In India Tag: Job Sr Staff/Staff/Senior Engineer– IP Design Verification position at Renesas Electronics


Date2026-03-26T17:20:34.013Z bot
Renesas Electronics Sr Staff/Staff/Senior Engineer– IP Design Verification
Experience: General
Pattern: Full-time
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loacation Bengaluru, Karnataka, India
loacation Bengaluru, Kar..........India
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Job DescriptionRenesas has a growing presence in India with HC approaching 1000+ and significant presence with active government and university collaboration as well as OSAT footprint (JV with CG India). With the growing importance of India as a market (Growing semiconductor market and government goals / mandates of localization needs) and talent hub, our division’s (India for India) mission is to grow India market. We aspire to create products (SoCs, Software, Power and Analog chips etc) which serve needs for local market. Renesas is a leading electronics supplier globally, and this is a unique opportunity to directly influence the future products which will be offered to our customers in a new, fast growing and large Indian market with specific needs and applications.We are seeking a highly experienced IP Design Verification Engineer to join the Verification R&D team at Renesas. In this role, you will be a part of team responsible for SOC verification, ensuring first‑pass silicon success through building verification environment from scratch using best in class methodologies, metric‑driven verification, and intelligent coverage convergence using AI tools.You will play a key technical role in defining verification strategies, architecting testbenches, defining Test Plans tracing Requirements, driving coverage closure using advanced automation and AI‑assisted techniques, and collaborating closely with Architecture, RTL, chip top, and Validation teams to deliver high‑quality, reusable IPs for next‑generation microcontrollers and microprocessors.Responsibilities:Be a part of end‑to‑end verification execution for SOC owning complex digital IP’s and subsystems from specification to sign‑offDefine and drive IP‑level verification strategies, including test plans, coverage models, and closure criteriaDevelop scalable, reusable UVM‑based verification environments for IP and subsystem verificationLead functional, code, assertion, and cross‑coverage closure, ensuring high‑quality sign‑off with clear metricsApply AI/ML‑assisted verification techniques to accelerate coverage convergence, identify stimulus gaps, and optimize regression efficiencyDrive constraint random and directed test methodologies for thorough protocol, corner‑case, and stress verificationCollaborate with RTL, Architecture, Emulation, and SoC Verification teams to ensure seamless IP integrationReview IP specifications and work with architects to translate requirements into robust verification plans and checkersDevelop and deploy advanced checkers, scoreboards, assertions (SVA), and protocol monitorsWork with EDA vendors to evaluate and adopt next‑generation verification, coverage, and analytics toolsMentor junior engineers and promote best‑in‑class verification practices and continuous improvementSupport Gate‑Level Simulation (GLS), low‑power verification, and post‑silicon debug when required.Ensure IP deliverables meet quality, schedule, and reusability expectations for SoC integration.

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