Staff Design Verification Engineer job opportunity at Renesas Electronics.



Date2026-03-04T06:31:14.568Z bot
Renesas Electronics Staff Design Verification Engineer
Experience: General
Pattern: Full-time
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degreeMBA
loacation Ho Chi Minh, Vietnam
loacation Ho Chi Minh....Vietnam
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Job DescriptionDo design verificationCreate Vplan (checking item)Write test programExecute test programConfirm verification resultJob requirements:Good experience in verification skill set.Experience in Vplan (verification plan) making from TS (target specification)Experience in task pattern (C language, ASM ) from VplanExperience in conduct verification result including coverage judgementFamiliar with simulator/debuger VCS/Verdi/XLM/IndagoKnowledge about SystemVerilog and UVMKnowledge about AMBA protocol: AHB, APB, AXI is a must.Basic knowledge of Formal verification, SVA, TCL.Have knowledge about assembly, C/C++, Verilog languages.Knowledge about Functional Safety, ISO26262 is a plusProvide transparent information, be agile in daily operations.Communicate fluently with teams and customers with a global mindset.Be innovative with excellent ideas in design and/or work-process optimization.Manage daily work, lead design team as an owner

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