Staff Engineer, ASIC Development Engineering (Front End CAD -RTL Integration, Lint, CDC) job opportunity at SanDisk.

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Date2026-04-29T14:59:13.069Z bot
SanDisk Staff Engineer, ASIC Development Engineering (Front End CAD -RTL Integration, Lint, CDC)
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ASIC Development Engineering (Front End CAD -RTL Integration, Lint, CDC)

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degreeGeneral
loacation Bengaluru, Karnataka, India
loacation Bengaluru, Kar..........India
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Job DescriptionAbout the RoleSanDisk's ASIC team builds state-of-the-art memory controllers that power world-class NAND Flash products used globally at massive scale. The Design Enablement team enables the Technology, Methodology, and Flows to ASIC design teams to deliver best-in-class products. As the Front End CAD/Methodology Engineer, you will play a pivotal role in developing and delivering robust RTL design methodologies on cutting-edge technology nodes, enabling best-in-class quality and productivity.This role is ideal for a seasoned front-end methodology leader who enjoys solving complex RTL integration challenges, working closely with design teams, and driving innovation across flows, tools, and automation.Key ResponsibilitiesRTL Integration & Assembly: Develop and maintain robust RTL integration flows, including IP stitching, hierarchical assembly, and top-level SoC integration methodologies.LINT Methodology: Architect and maintain comprehensive RTL linting flows using industry-standard tools (e.g., Synopsys SpyGlass, Cadence HAL, Siemens Questa AutoCheck) to ensure coding style compliance, synthesizability, and design quality.CDC (Clock Domain Crossing) Verification: Define and enforce CDC verification methodologies, including:Structural CDC analysisSynchronizer verificationProtocol checking and metastability analysisCDC coverage closure and signoff criteriaRDC (Reset Domain Crossing) Verification: Own and evolve RDC verification flows to ensure proper reset synchronization, reset sequencing, and reset-related functional correctness.ECO (Engineering Change Order) Flows: Develop and support RTL and netlist ECO methodologies for late-stage design changes, ensuring minimal impact on timing, area, and verification closure.Early PPA Estimation: Implement and maintain early Power, Performance, and Area (PPA) estimation flows on RTL to enable architecture exploration and design trade-off analysis before synthesis.Flow Automation & Infrastructure: Develop scripts, automation frameworks, and regression infrastructure to improve flow robustness, repeatability, and productivity across multiple ASIC programs.Shift-Left Methodologies: Drive correct-by-construction and shift-left approaches to catch RTL issues early, reducing iteration cycles and accelerating design closure.Tool Qualification & Evaluation: Lead tool evaluation, qualification, and deployment for front-end CAD tools; work with EDA vendors to resolve issues and drive feature enhancements.Collaboration: Work closely with RTL designers, verification engineers, synthesis teams, and physical design teams to identify recurring issues and introduce automation, checks, and best practices.

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