Technologist Engineer, ASIC Development Engineering (ASIC Verification) job opportunity at SanDisk.

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Date2026-03-31T06:17:11.536Z bot
SanDisk Technologist Engineer, ASIC Development Engineering (ASIC Verification)
Experience: General
Pattern: Full-time
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ASIC Development Engineering (ASIC Verification)

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degreeGeneral
loacation Bengaluru, Karnataka, India
loacation Bengaluru, Kar..........India
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Job DescriptionThe SoC Development team is seeking highly motivated engineers to join a team of experienced engineers working on the development of advanced controller SoCs.As a Technologist Verification Engineer in the SoC Development Team, you will be responsible for planning, architecting, and executing verification strategies to validate complex hardware in System-on-Chip (SoC) ASICs. Your work will enable industry-leading data storage control SoCs deployed into high-volume consumer and enterprise products.The growing diversity of data creates an exponential number of new possibilities – for the world, our company, and you. You’ll be part of a team driving the innovations necessary to outpace new demands and challenges everywhere data lives, from sensors to mobile devices to the cloud. We’ve only started to scratch the surface of what data can do. You can help unlock its full potential.Essential Duties and ResponsibilitiesOwnership: End-to-end ownership of one or more subsystems or SoC verification flows, including planning, execution, and closureMentorship: Experience mentoring junior and mid-level engineers, reviewing their test plans, code, and coverage.Define verification strategy, create detailed test plans, and develop robust test benches for SoC verification.Collaborate with architects, RTL designers, and pre- and post-silicon verification teams to ensure end-to-end verification coverage.Develop and run UVM/SystemVerilog-based verification environments.Write, run, and debug C-based tests on SoCs; processor and embedded software knowledge is a must.Define and achieve functional and code coverage goals; track and close coverage gaps.Run, debug, and sign off gate-level simulations with SDF annotation.Develop and validate functional patterns for ATE (Automatic Test Equipment).Debug complex issues across multiple domains (digital logic, firmware, timing, DFT).Participate in IP and subsystem-level integration verification and ensure smooth transition to SoC-level verification.Support low-power verification using UPF and ensure power intent validation.Automate regression setup, execution, and result analysis using scripting languages (Python, Perl, TCL, etc.).Contribute to verification methodology improvements, reusable environments, and verification infrastructure scalability.Work closely with validation and bring-up teams to ensure test portability from pre-silicon to post-silicon.

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