Senior Principal Engineer, RTL ASIC Design job opportunity at Marvell Technology, Inc..

Home Jobs In India Tag: RTL ASIC Design Senior Principal Engineer, RTL ASIC Design position at Marvell Technology, Inc.


DatePosted 4 Days Ago bot
Marvell Technology, Inc. Senior Principal Engineer, RTL ASIC Design
Experience: 18-years
Pattern: Full time
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RTL ASIC Design

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loacation Bangalore, India
loacation Bangalore....India
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About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Custom and Compute Solutions Business Unit closely collaborates with strategic customers in the development of advanced and highly complex SoCs, from architecture and design all the way through layout, packaging, prototype validation and production ramp up. What You Can Expect Methodology Development Design and implement robust workflows for design, verification, and automation. Establish best practices, standards, and documentation for methodology adoption. Continuously evaluate and refine methodologies to improve efficiency and scalability. AI Integration Apply machine learning and AI techniques to optimize design flows, resource allocation, and problem‑solving. Develop predictive models and intelligent tools to assist engineers in decision‑making. Collaborate with cross‑functional teams to identify opportunities for AI‑driven improvements. Tool & Infrastructure Management Work with CAD/EDA teams to integrate methodologies into existing toolchains. Automate repetitive tasks using scripting languages (Python, Perl, TCL, Shell). Ensure compatibility and interoperability across tools and platforms. Collaboration & Support Partner with design, verification, and CAD teams to deploy methodologies effectively. Provide training and support to engineers on new workflows and AI tools. Act as a liaison with vendors and research partners for tool evaluation and innovation. Innovation & Research Stay updated on emerging AI/ML techniques and industry trends. Propose and prototype new approaches to enhance design productivity. Contribute to long‑term strategy for AI adoption in engineering methodologies.   What We're Looking For Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field. 18+ years of experience in design automation, methodology development, or AI/ML applications in engineering. Strong programming and scripting skills (Python, TCL, Shell, C++). Hands‑on experience with EDA tools and design flows (front‑end and back‑end). Solid understanding of machine learning concepts and practical applications. Excellent problem‑solving, communication, and collaboration skills. Preferred Skills Experience with deep learning frameworks (TensorFlow, PyTorch). Knowledge of semiconductor design processes (RTL‑to‑GDSII, verification, DFM). Familiarity with cloud computing and distributed systems. Exposure to data analytics and visualization tools. Strong programming and scripting skills (Python, TCL, Shell, C++). Hands‑on experience with EDA tools and design flows (front‑end and back‑end). Solid understanding of machine learning concepts and practical applications. Excellent problem‑solving, communication, and collaboration skills. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Interview Integrity  To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-CP1

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