Senior Signal Integrity / Power Integrity (SI/PI) Engineer job opportunity at Arista Networks.

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Date2026-04-08T18:25:12.400Z bot
Arista Networks Senior Signal Integrity / Power Integrity (SI/PI) Engineer
Experience: General
Pattern: Full-time
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loacation Santa Clara, California, United States
loacation Santa Clara, C..........United States
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Job DescriptionWho You'll Work WithArista’s cutting-edge Ethernet and optical networking platforms are built to push the limits of performance, density, and power efficiency. This wouldn’t be possible without our Signal Integrity (SI) and Power Integrity (PI) engineers who design, simulate, and characterize interconnects enabling the fastest SerDes technologies in the industry. We’re looking for a Senior Signal Integrity / Power Integrity Hardware Engineer to join our Hardware Design team at our headquarters in Santa Clara, CA. In this role, you’ll work at the intersection of advanced simulation, next-generation SerDes (112G/224G/448G PAM4), and innovative routing, packaging, and power delivery techniques. Your work will directly influence the architecture and layout of Arista’s next-generation Ethernet and optical systems for hyperscale, AI, and cloud networking.What You'll DoPerform 3D EM design and simulation of high-speed interconnects (channels, vias, packages, and connectors) for 112G/224G PAM4 SerDes using tools such as Ansys HFSS, SiWave, and Cadence Sigrity.Develop and validate test vehicles to characterize next-generation PCB materials, packages, and interconnects.Conduct S-parameter and time-domain measurements (VNA, TDR, BERT) to extract channel performance and validate modeling correlation.Perform link-level analysis for advanced standards (Ethernet 800G/1.6T, PCIe Gen6/Gen7, CXL) using tools such as Keysight ADS or Cadence SystemSI.Collaborate closely with hardware, mechanical, and packaging teams to optimize stack- up, breakout, and routing strategies for high-density designs.Research and prototype novel materials, backplane concepts, and low-loss interconnect topologies to meet next-generation performance targets.Support bring-up and debug of production boards, working cross-functionally to root-cause SI/PI issues.

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