Senior Optical Signal Integrity / Power Integrity (SI/PI) Engineer job opportunity at Arista Networks.

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Date2026-04-10T17:25:44.703Z bot
Arista Networks Senior Optical Signal Integrity / Power Integrity (SI/PI) Engineer
Experience: General
Pattern: Full-time
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degreeGeneral
loacation Santa Clara, California, United States
loacation Santa Clara, C..........United States
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Job DescriptionWho You'll Work WithYou’ll work closely with hardware architects, ASIC vendors, layout, packaging, and optical teams to co-optimize performance, manufacturability, and reliability for state-of-the-art networking hardware. What You'll Do Arista Networks is seeking a Senior Optical Signal Integrity / Power Integrity (SI/PI) Engineer to lead the design, simulation, and validation of high-speed electrical interconnects and power delivery networks (PDNs) for next-generation optical modules and engines — including 1.6T, and emerging high density platforms using 224G, and 448G signaling. This position is critical in ensuring system-level performance across advanced photonic systems through robust SI/PI design and validation.Lead signal integrity (SI) and power integrity (PI) efforts for high-speed optical transceiver modules, high density optical interconnect platforms.Design and simulate high-speed channels up to 448G per lane (e.g., 224G/448G PAM4) across PCBs, packages, and connectors.Perform pre- and post-layout SI/PI simulations using tools like Ansys HFSS, Keysight ADS, Cadence Sigrity, and SiSoft QSI.Develop and validate PCB stackups, via structures, high-speed breakout regions, and connector transitions to meet compliance with IEEE, CEI, and MSA standards.Work closely with electrical, optical, and layout teams to define routing constraints, reference plane designs, and return path continuity for minimal signal degradation.Design and optimize PDNs to meet target impedance, minimize noise coupling, and support fast transient loads for high-speed DSPs and ICs.Provide SI/PI layout guidelines to PCB designers and review placement/routing for high-speed paths and power domains.Collaborate with validation teams to perform measurements (TDR, VNA, eye diagram, jitter, BER) and correlate with simulation models.Engage with ASIC, connector, and packaging vendors to support co-design and channel optimization across multiple integration layers.Drive root cause analysis of SI/PI-related issues during validation and production builds.

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